Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics and Fpgas Using Vhdl or Verilog
This book is the Electronic Engineers' comprehensive VHDL/Verilog modeling guide for ASIC and FPGAs. This book describes, and shows by practical example, how to design ASIC and FPGA devices using the two industry standard hardware description languages, VHDL and Verilog. The emphasis is on RTL modeling using synthesis within a top-down design methodology.
Table of Contents
ASIC and FPGA devices
Top-Down Design Methodology
Hardware Description Languages (HDLs)
Design Automation Tools
HDL support for synthesis
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